1. Field of the Invention
The present invention relates to a memory device and a manufacturing method thereof. More particularly, the present invention relates to an electrically erasable programmable read-only memory (EEPROM) cell and memory device that can be compatible with high operational voltage component and low operational voltage component, and the manufacturing method thereof.
2. Description of Related Art
Conventionally, electrically erasable programmable read-only memory (EEPROM) has the advantages of being programmable, erasable and the stored data being retainable even the power to the device is removed. In addition, EEPROM is also a kind of non-volatile memory. Therefore, EEPROM is very suitable for being integrated in a logic or mixed mode integrated circuits (IC) to enhance the auto-recovery or auto-adjustment function of the logic or mixed mode IC.
FIGS. 1A and FIG. 1B are schematic cross-sectional views illustrating a manufacturing process of a conventional EEPROM. Referring to FIG. 1A, in the manufacturing process of a conventional EEPROM, a tunnel layer 102, a polysilicon floating gate layer 104, an inter-gate dielectric layer 106 and a polysilicon control gate layer 108 are formed on a substrate 100 sequentially. Then, referring to FIG. 1B, the layers described above are patterned to form a stacked gate structure 110, and a source region 112a and a drain region 112b are formed in the substrate 100 beside two sides of the stacked gate structure 110.
However, in the manufacturing process described above, at least two polysilicon layers shall be disposed to form the floating gate and the control gate respectively. In addition, the two polysilicon layers of the memory cell and the gate of the metal oxide semiconductor (MOS) component of the peripheral circuit area are not at the same level of height. Therefore, the integration of the memory cell with the peripheral circuit is difficult.
In addition, the operation voltage of a conventional EEPROM is generally less than 12V. Therefore, the integration of EEPROM with high operational voltage component and low operational voltage component is difficult.
Furthermore, a conventional EEPROM cell is generally formed in an isolated well region; thus the EEPROM cell may be operated independently. Accordingly, the EEPROM cell can not share the same well region with the high operational voltage component and the low operational voltage component. Therefore, it is difficult to integrate an EEPROM cell with high operational voltage component and low operational voltage component.